module sin_str(
    input sys_clk,
    input rst_n,
    input sw1,sw2,sw3,sw4,
    output  wire [10:0] data
    );
    
parameter  fre_value_100=32'd33;//100频率
parameter  fre_value_1k=32'd336;//1k频率
parameter  fre_value_3k=32'd2576980;//30k频率
parameter  fre_value_10k=32'd858993;//10k频率

reg     [31:0] fre_cnt;
wire    [10:0] addr;  

    
always@(posedge sys_clk or negedge rst_n)//32bit的相位累加器
begin
    if(!rst_n)
        fre_cnt <= 32'd0;
    else  if(sw1==1'b0)
        fre_cnt <= fre_value_100 + fre_cnt;
    else if(sw2==1'b0)
        fre_cnt <= fre_value_1k + fre_cnt;
    else if(sw3==1'b0)
        fre_cnt <= fre_value_3k + fre_cnt;
    else if(sw4==1'b0)
        fre_cnt <= fre_value_10k + fre_cnt;
    else 
       fre_cnt <= fre_value_1k + fre_cnt; 
end


assign  addr =  fre_cnt[31:24];   
 
rom	rom_inst (
	.address ( addr ),
	.clock ( sys_clk ),
	.q ( data )
	);
endmodule
